摘要
为了提高D触发器的速度、降低功耗、缩小面积,本文对常用D触发器进行分析,综合各自优缺点,优化最高频率,设计出一款新型带清零的半静态D触发器,采用华润上华0.6μmN阱CMOS工艺,版图面积为46.500×40.350(μm)。该触发器的最高频率为356MHz,运用她构成二分频器并仿真成功。
For faster speed, lower power and smaller size,this paper analyzes several used D flip-flops.For the highest frequency and synthesizing their advantages and disadvantages, we design a new type D flip-flop of semi-static and clear.With CSMC 0.6gmN well CMOS process, the layout area is46.500 × 40.350（μm）.The maximum trigger frequency is 356MHz.Using it we constitute the second divider and simulates successfully.
出处
《电子世界》
2012年第7期147-149,共3页
Electronics World
关键词
D触发器
半静态
清零
版图
D flip-flop, semi-static, clear, layout
