摘要
介绍了一种采用基于FPGA状态机的设计方法,实现了对数字图像直方图实时统计功能。设计采用层次化、模块化的设计思想。所有模块用VHDL语言设计,由Modelsim仿真和集成开发环境QuartusII9.0综合。通过软件仿真和实际硬件电路验证,该设计正确可行,具有较好的应用价值。
A real - time histogram statistics design based on FPGA is introduced in this paper. Mealy state machine is used in this design which features with hierarchy and modularization. All software modules are programmed in VHDL. Simulation is worked out with Modelsim and the integrated development environment is Quartus II 9. 0. Through the software simulation and hardware test,the results show that the design is correct and feasible.
出处
《电视技术》
北大核心
2012年第7期24-25,41,共3页
Video Engineering
