摘要
随着曼彻斯特码的应用场合不断扩展,对曼彻斯特编解码的研究与应用也在不断深入和扩展,基于CYCLONE II系列FPGA芯片,利用VHDL硬件描述语言和Quartus II 9.0开发环境,完成了曼彻斯特编解码模块的设计。在编解码模块的复位单元中使用了异步复位、同步释放的双缓冲电路,降低了异步复位发生亚稳态的概率和减少了同步复位的资源消耗。经过数字仿真波形分析,验证了设计方法的可行性和正确性。
With the application field of Manchester code constantly expanding,the study of Manchester encoding and decoding is also constantly in-depth and extended.Using VHDL hardware description language to implement the encoding and decoding function of Manchester code,based on FPGA chip of Altera company CYCLONE II series,in Quartus II 9.0 development environment.The double buffer circuits of asynchronous reset and synchronous release are adopted in reset module of encoding and decoding modules,which not only can solve the issue of synchronous reset resource consumption,but also reduce the occurring probability of asynchronous reset metastable state.The proposed design scheme is proved correctly through the corresponding digital simulation.
出处
《机电产品开发与创新》
2011年第6期148-150,共3页
Development & Innovation of Machinery & Electrical Products
基金
江苏省自然科学研究基金项目(BK2008367)
南京工程学院创新基金项目(CKJ2009004)
先进数控技术重点实验室开放基金项目(KXJ07117)
