摘要
设计了一个高精度、低功耗音频Σ-Δ数模转换器(DAC)中的模拟部分电路.该DAC采用4 bit量化,不仅增强了调制器的稳定性,减小了功耗和占用面积,而且降低了系统对后端低通滤波器的要求.讨论了电路各模块的实现方法,并详述了开关电容、带隙基准源等产生非线性的关键模块的设计技术.基于SMIC 0.18μm混合信号CMOS工艺进行了流片验证,测试结果表明:芯片最大信噪失真比达89 dB,动态范围为96 dB,总功耗为19.1mW,其中不含缓冲器的功耗仅9.1 mW,样片良率为90%,实现了高精度、低功耗的性能.
An analog circuit with high resolution and low power in a sigma-delta（Σ-Δ） digital-to-analog converter（DAC） was designed.By adopting 4-bit quantized technique,this DAC not only enhances the stability of the modulator,reduces the power consumption and the occupied area,but also reduces the system requirements for the back-end low-pass filter.Realizing methods of different modules were given,besides,design techniques in crucial modules that generated non-linearity,such as switched-capacitors and bandgap reference,were discussed.This design was fabricated in SMIC 0.18 μm mixed-signal CMOS process and verified.The measured results showed that the chip had a peak SNDR of 89 dB and a 96 dB dynamic range（DR）,and consumed a total power of 19.1 mW,and this value droped to 9.1 mW without buffers.Moreover,the prototype yield was 90%,achieving high precision and low power dissipation.
出处
《浙江大学学报（工学版）》
EI
CAS
CSCD
北大核心
2011年第9期1571-1575,1581,共6页
Journal of Zhejiang University：Engineering Science
