摘要
Motion Estimation （ME） is considerate one of the most important compression methods. However, ME involves high computational complexity. The main goal is to reduce power conception and the execution time without reducing image quality. In this paper, the authors have proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method is based on the stoppable clock models. The architecture has been simulated and synthesized with VHDL and ASIC （CMOS 45 nm）. Synthesize results show that the proposed architecture reduces the power consumption and achieves a high performance for real time motion estimation.
