摘要
为了降低组合电路内建自测试的测试功耗，提出了一种基于格雷码的测试序列分配算法．分组式格雷码序列和种子序列相异或生成单跳变测试序列，根据电路的基本输入权重，合理分配测试序列位，减少了电路内部节点的跳变，有效降低了电路的测试功耗．该算法应用在改进的布斯二阶乘法器的自测试中，根据不同的数据通道位宽，相对于传统自测试架构，测试功耗降低了35．6％～43．7％，并且不影响乘法器的性能．对ISCA85基准电路的测试结果表明，该算法降低了测试功耗，具有高的故障覆盖率和少的测试长度，与LFSR相比功耗下降了59．3％～97．3％，并且硬件开销小．实验结果表明，该算法有效降低了组合电路的测试功耗，特别适合于系统级芯片内部模块的内建自测试．
An algorithm is presented to reduce the power dissipation during test application for combinational circuits tested using built in self-test（BIST）. The test sequence is generated by logic XOR operation between Group Gray code sequence and its canonical seeds to ensure that it is a single input change （SIC） sequence. According to the primary input weights of circuit, this algorithm properly assigns the Test Pattern Generator （TPG） outputs to the circuit based on the character of Gray code. The algorithm has been used for Modified Booth Multiplier（MBM）. As compared to the conventional BIST scheme, the achieved reduction of power dissipation is from 35.6% to 43.7% depending on the size of the MBM. Testing results on the ISCAS＇85 benchmark circuit show that the algorithm can achieve low power eonsumption and higher fault coverage while using less test patterns, and the power consumption is reduced by 59.3% -97.3% compared with LFSR at very small area overhead. Experimental results indicate that the proposed algorithm is very effective and applicable for low power BIST of embedded cores of systems on chip.
出处
《计算机学报》
EI
CSCD
北大核心
2011年第9期1697-1704,共8页
Chinese Journal of Computers
基金
国家自然科学基金(60605009)资助~~
关键词
功耗
内建自测试
权重
测试序列
格雷码
power dissipation
built in self-test （BIST）
weight
test pattern
Gray code
