摘要
提出了一种基于FPGA的网络通讯流量模糊控制器的实现方法.根据一个基于缓冲管理模式和模糊逻辑的网络通讯流量模糊控制器模型,提出了系统总体实现结构和模糊化、模糊推理和去模糊化模块的实现方法,给出了Verilog HDL程序实现结果,包括功能仿真结果、逻辑资源消耗和系统最高时钟频率.为了提高系统的处理速度,系统结构设计中采用了流水线技术和并行技术,并采用了专门设计的乘法器和除法器.实验结果验证了本控制器结构设计的有效性和程序设计的正确性,系统的最高时钟频率达273.22 MHz.本系统可以应用于ATM和IP网络的流量控制,修改后也可应用于智能交通控制.
A FPGA-based implementation of the fuzzy controller for network traffic is proposed. According to the controller model based on buffer management mode and fuzzy logic, the modules of fuzzification, fuzzy inference and defuzzification are implemented following the overall architecture design. Besides the functional simulation results of Verilog HDL programming, the logic resource consumption and the maximum system clock frequency are provided at the same time. In order to improve the system processing speed, not only the pipeline and parallel strategies but also the specially designed multiplier and divider are adopted. Experimental results demonstrate the effectiveness of the controller design and the correctness of programming, the maximum clock frequency of the system is up to 273.22 MHz. The designed system can he applied to ATM and IP network traffic control or to intelligent transportation control with modification.
出处
《测试技术学报》
2011年第5期421-426,共6页
Journal of Test and Measurement Technology
基金
湖南省教育厅科研项目(09C333)
中国包装总公司科研项目(2008-KJ07)
关键词
网络通讯管理
模糊控制器
FPGA
并行处理
流水线
network traffic managing
fuzzy logic controller
FPGA
parallel processing
pipelining
