摘要
本文给出一种构造D＝4SM阵列编码的图论方法。它是基于文献[1]的基础之上，利用生成Hamilton逻辑路径的顶点排列与SMn（4）阵列码的对应关系，找出一种简便的生成算法。实现不限维地，方便快速地构造SMn（4）阵列编码。
Based on graph theory, A method for D=4SM array coding is proposed. This work is the succession ofreference paper[1], Starting from the relation between the vertex arrangement for generating Hamilton logical path and SMn(4)array codes, a simple and straightforward code generating algorithm is derived. Using this algorithm, SMn(4) array codes canbe quickly realized without limiting the number of dimensions.
出处
《电路与系统学报》
CSCD
1999年第4期62-67,共6页
Journal of Circuits and Systems
关键词
阵列编码
逻辑通路
图论
算法
SM^n(4) array codes, Half Hamilton logical path, Existing topology condition, Generating algorithm
