摘要
为了缩短卷积编码器设计周期,使硬件设计更具灵活性,在介绍卷积编码器原理的基础上,论述了一种基于可编程逻辑器件,采用模块化设计方法,利用VHDL硬件描述语言实现CDMA 2000系统前向链路卷积编码器的方法,给出了在QuartusⅡ软件下的仿真结果,并在FPGA器件上验证实现。仿真和实验都证明了这种方法的可行性和正确性。
In order to shorten the design cycle and make the hardware design more flexible, a design method of convolutional encoder based on FPGA is proposed. An implementation of CDMA 2000 system convolutional encoder based on FPGA, modular design and VHDL hardware description language is discussed. The simulation results of the convolutional encoder in Quartus Ⅱ software platform are given and verified in FPGA device. The feasibility and validity of this approach is proved by simulation and practice.
出处
《现代电子技术》
2011年第13期24-26,共3页
Modern Electronics Technique
