摘要
信号完整性(SI)是高速电路设计面临的一个主要问题。对109 Hz以上高速信号的信号完整性问题从原理上进行了详细分析,并针对损耗、串扰、反射等因素提出了改善信号完整性的方法。在高速串行RapidIO总线背板的设计中,探索出一套利用HyperLynx工具进行仿真分析和设计验证的方法,即利用前仿真工具LineSim对影响信号完整性的主要参数进行评估,形成设计指导数据;利用后仿真工具BoardSim对布线后的高速背板进行验证,从理论上证明了高速串行RapidIO总线背板的设计是可行的。
Signal integrity（SI） is a key problem in design of high speed bus.In this paper,the SI of high speed bus signal above 109Hz is analyzed,and ways to improve SI are put forward with respect to the influences of loss,crosstalk and reflection on SI.In the design of the high speed backboard,with the help of HyperLynx,a method for simulation and validation is proposed,in which LineSim is adopted to evaluate the main parameters affecting SI and achieve guiding data for design,and BoardSim is also adopted to validate the designed high speed backboard.The feasibility of the de-signed high speed serial rapidIO bus backboard is theoretically proved.
出处
《鱼雷技术》
2011年第3期167-171,共5页
Torpedo Technology
