摘要
根据3GPP协议规定,提出一种适于FPGA实现的解决方案。采用分而治之和WFTA的算式分解,最大限度地减少DFT的运算量;采用块浮点动态截取多余位宽,减少系统面积;运用4个双端口RAM读写,使系统能运行在流水线结构;采用对称结构存储每一级的旋转因子,最大化共享因子。
The aim of the paper is to give an FPGA implementation for the DFT.Use divide and conquer and WFTA to decomposition the formula,maximum reduction computation of DFT.Use block floating point to dynamic interception bits wide,then reduce system size.Use 4 dual-port RAM to read and write,then the system can run in pipeline.Use Symmetrical structure stored the twiddle factor,maximize sharing factor.
出处
《微型机与应用》
2011年第12期64-67,共4页
Microcomputer & Its Applications
