摘要
在ADC中应用Dither技术,可以减小ADC的量化误差、在统计上减小DNL误差、提高ADC的分辨率,但是却存在输入信号较大时,引入Dither噪声后可能发生信号溢出的问题。在此针对流水线ADC分级结构的特殊性,提出一种流水线ADC结构,在普通流水线ADC的第一子级后增加残差改变模块,在改进的流水线ADC中可以引入一定幅度范围内的Dither而不发生溢出。最后,在Simulink中搭建流水线ADC的行为级模型进行了仿真验证,证明所提出的流水线ADC结构在保证引入Dither后信号不会溢出的同时,也能有效地提升其SFDR性能。
Application of the dither technology in,ADC is possible to reduce the quantization error of ADC and DNL error in statistics and improve its dynamic performance.but there is a problem that the signal overflow may occur when the amplitude of input signal is large.A pipelined ADC structure is proposed according to the characteristic of pipeline ADC, that is, a modual for resdual error modification is added behind the firtst sub-stage of pipelined ADC. In the improved pipeline ADC structure a Dither which is in the limited range can be introduced without appearance of the signal overflow. It proves that the new pipelined ADC structure can prevent the signal overflow caused by Dither addition and improve the spurious-free dynamic range（FSDR）by modeling the pipelined ADC system in simulink.
出处
《现代电子技术》
2011年第10期160-162,共3页
Modern Electronics Technique
基金
国家"863"目标导向基金资助项目(2009AA01Z259)
