摘要
Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.
基于0.13μmCMOS技术设计了一个应用于无线传感网频率合成器、电源电压为0.5V的鉴频鉴相器.它的功能是比较输入信号的频率和相位差,并输出一个与该差值成比例的电压.因电源电压是0.5V,所以该电路采用低阈值晶体管.为了增大相位误差的检测范围和提高最大工作频率,该电路采用了脉冲锁存的结构.当输入信号频率为2MHz时,测得的相位误差检测范围为-358°～358°.与传统数字鉴频鉴相器相比,该电路具有较快的捕获速度.当输入信号的频率为2MHz且相位误差为0°时,电路的功耗为1.8μW,并且最大工作频率为1.25GHz.
基金
The National High Technology Research and Development Program of China (863 Program) (No. 2007AA01Z2A7)
Program for Special Talents in Six Fields of Jiangsu Province
