摘要
An English speech recognition system was implemented on a chip, called speech system-on-chip （SoC）. The SoC included an application specific integrated circuit with a vector accelerator to improve performance. The sub-word model based on a continuous density hidden Markov model recognition algorithm ran on a very cheap speech chip. The algorithm was a two-stage fixed-width beam-search baseline system with a variable beam-width pruning strategy and a frame-synchronous word-level pruning strategy to significantly reduce the recognition time. Tests show that this method reduces the recognition time nearly 6 fold and the memory size nearly 2 fold compared to the original system, with less than 1% accuracy degradation for a 600 word recognition task and recognition accuracy rate of about 98%.
An English speech recognition system was implemented on a chip, called speech system-on-chip （SoC）. The SoC included an application specific integrated circuit with a vector accelerator to improve performance. The sub-word model based on a continuous density hidden Markov model recognition algorithm ran on a very cheap speech chip. The algorithm was a two-stage fixed-width beam-search baseline system with a variable beam-width pruning strategy and a frame-synchronous word-level pruning strategy to significantly reduce the recognition time. Tests show that this method reduces the recognition time nearly 6 fold and the memory size nearly 2 fold compared to the original system, with less than 1% accuracy degradation for a 600 word recognition task and recognition accuracy rate of about 98%.
基金
Supported by the National Natural Science Foundation of China and Microsoft Research Asia(No. 60776800)
the National Natural Science Foundation of China and Research Grants Council (No.60931160443)
the National High-Tech Research and Development (863) Program of China(Nos. 2006AA010101,2007AA04Z223,2008AA02Z414,and 2008AA040201)
