摘要
曼彻斯特编解码器是1553B总线协议的重要组成部分,其性能的好坏直接影响整个系统的通信质量。通过分析MIL-STD-1553B协议和GJB5186测试标准,制定出编解码器的设计规范。采用硬件描述语言(Verilog)设计电路,VCS对设计进行仿真,并利用Synplify Pro及ISE完成综合和布局布线的工作,最后载入Xilinx FPGA进行测试。在深入分析曼彻斯特码型特点的基础上,对编解码器的工作过程及逻辑电路结构进行详细介绍。提出的时钟分离电路比超前滞后数字锁相环更为简单有效。
Manchester codec is the essential part of MIL-STD-1553B bus protocol. The performance of the codec will di reetly affect the quality of the communication. The Codec specification was fixed by the analysis of MIL-STD-1553B bus pro tocol and the GJB5186 testing standard. The Codec circuit was implemented by Verilog HDL, simulated by VCS, synthesized by Synplify Pro, routed with ISE and tested by Xilinx FPGA hoard. On the basis of analyzing the characteristic of the Man chester code, the principle and the circuit structure of the codec are introduced in detail. The clock separation circuit intro duced in the paper is more simple and efficient than the lead lag digital PLL.
出处
《现代电子技术》
2011年第4期61-64,共4页
Modern Electronics Technique
