摘要
本文设计了一种面向视频处理的可重构处理阵列系统。从系统结构、存储器行为、阵列互连、处理单元结构和控制器等方面对系统进行了详细的介绍。为了对该系统进行验证,本文在RTL级对系统中的阵列部分进行了建模、仿真以及综合,得到了阵列的性能、面积等参数。而后将H.264解码器中的主要算法——整数余弦反变换映射到该阵列上,分析了该算法实现所需的时间。同时,本文还在系统级对同样的算法进行了设计和仿真,得到了同样规模的计算在系统级所需要的时间,对如何提升系统性能提出了建议——合理安排配置字写入、阵列配置以及原始数据输入,尽量使其与计算时间重叠。
This paper designs a reconfigurable computing array system for video processing. The system structure,memory,interconnection of the array,also the processing element and the controller are introduced in detail. For verification,the part of array is implemented in the RTL level. After simulation and synthesis flow,the performance and area of the array are analyzed. Moreover,this paper mapps the Inverse-ICT of H.264 decoder into the array and analyzes the time needed. Finally,the whole system is verified in the environment of SoC Designer with the same application. Compared with the RTL level simulation,suggestion for raise the system performance is proposed that is arranging the context word loading,array configuration and the data input properly,to maximize the time overlapped by computing.
出处
《微计算机信息》
2010年第31期95-97,共3页
Control & Automation
