摘要
介绍了在CSR同步加速器高频控制系统改进项目中,高频前端控制器的改进设计。根据系统改进的具体要求,采用DSP+FPGA双电路板的体系结构,对高频前端控制器各个部分做了详细的设计,并给出了具体的资源消耗结果和设计图。
It introduces the improvement design of RF front-end controller for improvement project of CSR syn-chrotron RF control system. According to specific demands of the improvement, we adopt the architecture including DSP ＋ FPGA and two printed circuit boards and design every part of the controller carefully. Then, resource cost and design schematic are also addressed.
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2010年第8期1055-1058,1066,共5页
Nuclear Electronics & Detection Technology
基金
CSR同步加速器高频控制系统改进项目
