摘要
在北京谱仪BESⅢ升级改造工程TOF触发子系统的设计中,提出了采用LVDS电平扇出触发处理结果的方案,以获得足够的驱动以及抗干扰能力。考虑到传输数据量非常大,为了节省空间以及提供传输效率,决定引入并串/串并转换传输技术并设计了相应的接收板对其进行深入研究。通过结合FPGA中FIFO的同步功能设计,成功实现了多通道LVDS并串/串并转换传输的同步接收,从而在一个9U VME背板总线后插数据传输模块上完成了全部TOF触发处理结果的高密度同步输出。同时也为复杂仪器系统中高速大量数据的实时同步传输和接收提供了一个可靠且高效的解决方案。
LVDS transmission is promoted for the output of TOF Trigger System at BESⅢ, which can provide enough driving capacity and noise immunity. Considering that there are a large amount of signals, parallel-to-serial/serial-to-parallel scheme is introduced so as to save space and get higher efficiency. A receiving board has been established for test and verification. Combined with FIFOs which are designed for synchronous purpose in FPGA, we successfully get the synchronous receiving of recovered data of multi-channel serial transmission. Thus we have accomplished the aim of fulfilling the fan-out of all the TOF trigger signals on a 9U VME rear transition module. It presents a very good reference solution to transfer mass signals synchronously with high speed in complex instrument systems actually.
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2010年第7期920-924,共5页
Nuclear Electronics & Detection Technology
基金
国家大科学工程北京正负电子对撞机升级项目BEPCⅡ
安徽高校“物理电子学”省级重点实验室资助
