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基于FPGA的OFDM时间同步系统串并结构设计

Design of Serial-Parallel Structure in OFDM Timing Synchronization System Based on FPGA
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摘要 时间同步技术是OFDM系统中影响其性能的关键技术之一;针对相关运算中使用较多并行乘法器导致硬件资源大量消耗的问题,提出了一种串并相结合乘法器的结构设计;该方案在很大程度上降低了硬件资源消耗的同时又保证了延时性,并基于硬件平台给出了相应的实现结构,在此基础上对结果进行了分析;仿真结果表明,该算法在多径信道环境下具有较高的时间同步精度,能够较大程度地降低硬件资源消耗,在实际系统中具有很好的利用价值。 Synchronization is one of the key technology of OFDM systems. Due to the conjugate multiplication module needing lots of parallel multipliers, the traditional algorithm will consume a lot of hardware resource. To solve this problem, a novel synchronization algo- rithm which combines serial multipliers and parallel multipliers is proposed in this paper. This algorithm can reduce consumption of hardware resources to a great extent, while maintaining timelag. Structure based on hardware platform is given, and the results based on this structure are analyzed. Simulation results show that under the condition of multi--path channel, our algorithm not only have high precision in timing --synchronization, but also can reduce the consumption of hardware resource. It can provide a good application value in actual system.
机构地区 西北工业大学第
出处 《计算机测量与控制》 CSCD 北大核心 2010年第7期1618-1620,共3页 Computer Measurement &Control
关键词 OFDM时间同步 共轭乘法 串并结合 OFDM timing synchronization conjugate multiplication serial--parallel combination
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