摘要
文章提出了利用信号时序检测方法监测电视信号的播出中断和非法干扰,采用FPGA设计实现对32路电视同步信号的实时检测,并依此设计出一个电视信号自动监测与报警系统;系统使用Verilog HDL语言进行硬件电路描述,使用Xilinx ISE9.1软件和ModelSim6.2仿真工具对FPGA设计进行配置和仿真,给出了硬件模块设计和部分软件代码;实验结果表明,系统达到了实用要求。
This paper presents a method of using time sequence detection to monitor the interruption and illegal disturbance in TV signals.The FPGA design is applied in real-time detection of 32 TV synchronous signals.Based on this design,an automatic TV signal monitoring and alarming system is constructed.The hardware circuit description of the system is performed with Verilog HDL,and the configuration and simulation are performed with Xilinx ISE9.1 and ModelSim6.2.The paper also introduces the hardware module design and partial software codes.Test results indicate that the design reaches its expected aims and can be put into practical use.
出处
《合肥工业大学学报（自然科学版）》
CAS
CSCD
北大核心
2010年第7期993-996,共4页
Journal of Hefei University of Technology：Natural Science
关键词
非法干扰
电视信号监测
同步信号检测
FPGA设计
illegal disturbance
TV signal monitoring
synchronous signal detecting
FPGA design
