摘要
为了降低SRAM的功耗,提出了一种优化的SRAM。对改变较快的输入端引入操作数隔离技术,对比较电路的多位数据进行总线数据分割;给较大的时钟网络增加门控时钟,引入多种电源控制模式并增加隔离逻辑;将SRAM64K×32分解为8个SRAM8K×32子块,由八选一逻辑通过各子块的片选信号相连,使得同时只有一个子块处于读写状态。将优化的SRAM64K×32应用到SOC中,并通过增加旁路逻辑来测试各部分功耗。该SOC经90nmCMOS工艺成功流片。测试结果表明,优化的SRAM64K×32功耗降低了29.569%,面积仅增加了0.836%。
In order to reduce power consumption of SRAM,an optimized SRAM was presented. Technology with isola tion of operation data was introduced into fast inputs,division of bus data was made to multiple bits of comparator; gating clock was added into big clock network, many modes of power control and isolation logic were increased; SRAM64K× 32 was separated into 8 sub blocks of SRAM8K × 32, which were connected with signals to select chip through logic of one selected from eight so that only one of sub blocks can be in read-write operation. The optimized SRAM64K× 32 was used in SOC and power consumption of each part was measured by adding bypass logic. The design was successfully implemented in 90nm CMOS process. The testing results indicate that power saving of the optimized SRAM64K×32 is 29. 569% and area only increased by 0. 836%.
出处
《计算机科学》
CSCD
北大核心
2010年第7期301-302,F0003,共3页
Computer Science
基金
863国家重点基金项目(2003AA1Z1410)
国家自然科学基金(60276028)资助
关键词
低功耗
操作数隔离
总线数据分割
电源控制模式
旁路逻辑
Low power, Isolation of operation data, Division of bus data, Mode of power control, Bypass logic
