摘要
介绍了基于功能块提取器（ＤＬＦＥ）工具的时序功能块提取工具和方法．整套工具用于从版图中构造层次化电路，以利于电路的验证和理解．时序功能块提取通过时序功能块的普遍特征来定位时序功能块，避免了手工定位的盲目性，大大加快了构造层次化电路的速度．实验证明，工具对时序模块的提取是十分有效的．
To construct hierarchical circuit from layout, properties of sequential module are utilized to extract sequential modules out of netlist. The work is based on DLFE (Digital Logic Functional block Extractor). With the tool's help, objectless manual searches of sequential module during the use of DLFE are avoided and construction of hierarchical circuit are greatly speeded.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
1999年第1期89-92,共4页
Journal of Computer-Aided Design & Computer Graphics
关键词
功能块提取
时序功能块
逻辑验证
集成电路
functional block extraction, sequential module, logic verification
