摘要
设计了一种由现场可编程逻辑阵列FPGA实现的ZVS条件下死区时间控制电路,该电路不仅可有效防止上下功率管的同时导通,而且能够减小功率级的损耗,降低放大器的谐波畸变率。阐述了所设计电路的特点和功能,并对其进行了功能仿真和静态时序分析。
A circuit was presented to control the deadtime in ZVS condition via FPGA, which not only can prevent effectively large shoot-through currents from passing through upper and lower power transistors at the same time, but also can reduce the dissipation of amplifier and THD. The features and functions was described and functional simulation and static timing analysis was presented also.
出处
《微型机与应用》
2010年第9期75-77,80,共4页
Microcomputer & Its Applications
