摘要
高精度的浮点乘加融合(FMA)部件一直是高性能微处理器设计追求的目标。提出了一种128位精度全流水FMA体系结构,采用10级平衡流水线,重点对超宽位的乘法器、加法器、前导零预测和规格化进行了流水优化。设计综合的结果表明,基于SMIC0.13μm工艺,该结构频率可以达到465MHz,比现有128位FMA性能提高了130%;在TSMC65nm工艺下,该结构的频率可达到1.075GHz,基本满足高性能计算的要求。
FMA（Fused Multiply-Add） with high precision is required in high performance microprocessors. A new 10 stages pipelined architecture of 128bit FMA is propesed. In this architecture, multiply, adder, IZA（leading Zero Anticipator） and normalization with large width data-paths were partitioned and optimized carefully to balance the latency at every pipeline stage. After designed and synthesized with SMIC 0.13um technology, the frequency of the FMA can reach 465MHz, which is about 130% better than previous 128hit FMA. Furthermore, its frequency can reach 1.075GHz with TSMC 65nm technology, which basically meets the requirements of the high performance computation.
出处
《国防科技大学学报》
EI
CAS
CSCD
北大核心
2010年第2期56-60,共5页
Journal of National University of Defense Technology
基金
国家自然科学基金重点资助项目(90707003)
关键词
浮点乘加融合
前导零预测
高性能微处理器
Fused Multlply-Add（ FMA ）
Leading Zero Anticipator（IZA）
high performance microprocessor
