摘要
纠错技术是现代通信系统不可缺少的技术,针对目前纠错码测试可重构性要求高和测试数据量大的特点,提出了一种针对纠错码的基于分层原理的软硬件联合测试平台。采用分层的设计结构,使得该平台具备高度的可重构性,能够在不同纠错码测试之间进行迅速重构。利用高速的PCI数据采集卡PCI-7300A在PC和FPGA之间进行数据传输,并在PC和FPGA端对数据进行分层封装和添加校验与确认—重传机制,以此保证数据高速、顺序、无差错地传输。通过利用该平台对多进制LDPC码进行测试,结果表明,在传输时钟为20MHz的时候,平台吞吐量达到446.83Mbit/s。
The error correcting technology is indispensable in modern communication system. In this paper, in order to meet the high reconfigurable requirement of current error correcting test, a new error correcting codes （ECC） test platform was proposed based on the layer principle and the hardware-software co-design. The layering design construction enables the platform of high reconfiguration ability, which reconfigures quickly between the different ECC. In order to ensure the high-speed, ordinal and error-free data transmission, high-speed PCI data collection card PCI-7300A was used to transmit data between PC and FPGA, and the data was packaged layeredly and the parity bit and confirm-retransmission mechanism was added between port of PC and FPGA. Through the testing of non-binary LDPC by using this platform, the results show that the throughput of the platform reach to 446.83 Mbps when the transmit clock is 20 MHz.
出处
《重庆邮电大学学报（自然科学版）》
北大核心
2010年第2期188-191,共4页
Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)
基金
福建省重点科技项目(2006H0039)
重庆市科委自然科学基金项目(CSTC
2007BB2387)~~
关键词
分层原理
纠错码
测试平台
PCI-7300A
可重构性
layering principle
error correcting codes （EEC）
testing platform
PCI-7300A
reconfigurable
