摘要
介绍了一种基于NiosⅡ嵌入式处理器实现的雷达监控系统,并详细说明了其可编程系统(SOPC)(system on programmable chip)的硬件构建过程和软件设计流程.本设计采用Cyclone Ⅱ系列FPGA作为核心硬件,在FPGA上构建了基于高性能32位嵌入式NiosⅡ处理器的片上SOPC;在NiosⅡ IDE环境下开发出SOPC的应用软件.与传统的监控系统相比,本方案拥有更高的集成度、更快的数据传输速度,以及较小的体积和功耗.
This study presents a radar monitoring and controlling system which is mainly based on the NiosⅡ CPU and introduces the hardware integration and software design flow of the system on programmable chip. The kernel of design is Cyclone Ⅱ family FPGA which supports the 32 bits high performance NiosⅡ CPU,and application software is developed in NiosⅡ IDE environment tool. Compared with the traditional monitoring and controlling system,the present design has capabilities of fast data transmitting,low power consumming,and high integration.
出处
《中国科学院研究生院学报》
CAS
CSCD
北大核心
2010年第1期63-69,共7页
Journal of the Graduate School of the Chinese Academy of Sciences
