摘要
根据不同环境对安全散列算法安全强度的不同要求,采用可重构体系结构的思想和方法,设计一种可重构的散列函数密码芯片。实验结果表明,在Altera Stratix II系列现场可编程门阵列上,SHA-1,SHA-224/256,SHA-384/512的吞吐率分别可达到727.853Mb/s,909.816Mb/s和1.456Gb/s。
According to different needs to security hash algorithms under different circumstances, this paper adopts the thought and method of the reconfigurable architecture, and designs a reconfigurable hash cryptographic chip. Experimental results based on FPGA of the family of Stratix lI of Altera Corporation show that the proposed system reaches throughput values equal to 727.853 Mb/s for SHA- 1,909.816 Mb/s for SHA-224/256, and 1.456 Gb/s for SHA-384/512 respectively.
出处
《计算机工程》
CAS
CSCD
北大核心
2010年第6期131-132,136,共3页
Computer Engineering
基金
国家"863"计划基金资助项目(2008AA01Z0103)
关键词
可重构密码芯片
安全散列算法
现场可编程门阵列
reconfigurable cryptographic chip
security hash algorithms
Field Programmable Gate Array（FPGA）
