摘要
提出了一种针对混合信号SoC中ADC的动态参数与静态参数测试的内建自测试方案.由于动态参数和静态参数在同一个测试电路中都能够得到测试,因此能够更加全面准确地反映待测器件的性能.通过对存储器和计算资源的合理配置和复用,将两种测试的激励产生和响应分析集成在一起,最大程度地减少了对电路面积的影响.整个设计在FPGA上实现,实验结果证明了其可行性.
A BIST scheme that can both characterize the dynamic and static parameters of ADC in mixed-signal SoC are proposed in this paper. The proposed scheme can fully characterize the ADC under test by integrating test capability of both dynamic and static test uniformly in one BIST circuit. Elemental operative units and memories for analog stimulus generation and response analysis are well organized and reused to reduce hardware overhead to the minimum. The pro- posed scheme is implemented in FPGA thereby validates the viability of the design.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第1期123-126,共4页
Microelectronics & Computer
