摘要
直方图均衡是一种基本的图像增强处理方法。传统的直方图均衡算法由于其复杂性,在硬件实现时往往需要FPGA和DSP的协处理,不仅耗费逻辑资源,而且实时性差,特别是在处理视频图像时,对处理速度的要求更高。为了使算法能够在FPGA上具体实现,文中对算法进行了改进,实现了直方图统计和均衡的并行执行,利用Verilog语言对算法进行了完全可综合的RTL级描述,在Linux系统上应用Ncverilog进行了编译仿真,并利用Synplify Pro8.2.1进行了综合,最后给出了仿真及综合结果。
Histogram equalization is a technique commonly used in image enhancement. For the complexity of the traditional HE algorithm, the co-process of FPGA with DSP is used when the algorithm is implemented on hardware, thus causing the waste of resource and time. Moreover, in the real-time processing of video image, the speed of processing is even more important. For the specific implementation of this algorithm on FPGA, some improvement of the traditional algorithm is made, and the parallel-process of HE statistic and equalization is thus realized. The RTL-level description of the algorithm by Verilog language is achieved. Then Ncverilog is used to assemble and simulate the code on Linux, while to synthesize it by Synplify Pro 8.2.1. Finally, the experiment results are given in this paper.
出处
《信息安全与通信保密》
2009年第12期72-74,共3页
Information Security and Communications Privacy
基金
国家自然科学基金资助项目(批准号:60672184)
