摘要
介绍一种基于FPGA的抢答器设计,给出了顶层电路原理图和主模块的部分VHDL源程序。利用MAX+PLUSⅡ开发平台完成了编译、仿真,并下载到EPF10K10LC84-4器件中进行测试。该抢答器不仅能实现互锁、自锁和倒计时功能,而且能用声音、数码管准确提示抢答的优先结果和犯规情况,具有广泛的应用前景。
This paper introduces the design of answering racer based on FPGA. The toplayer schematic and parts of VHDL source program are presented. Its encoding and simulation are compeleted with MAXq-PLUS II. The program is tested by EPF10LC84-4. The fimction of interlock, selflock and invert counter is performed with sound and BCD-TO-SEVEN-SEGMENT showwing the priority and rule-broken.
出处
《电脑与电信》
2009年第11期31-33,共3页
Computer & Telecommunication
基金
海南师范大学开放实验项目
项目编号:KFSY08043
