摘要
为了降低sigma-delta模数转换器功耗,针对应用于sigma-delta模数转换器环境的UMC 0.18μm工艺,提出1种由参考电压产生电路、预放大器、锁存器以及用作输出采样器的动态锁存器组成的新型高速低功耗的CMOS预放大锁存比较器。该比较器中输出采样器由传输门和2个反相器组成,可在较大程度上减少该比较器的功耗。电路采用标准UMC0.18μm工艺进行HSPICE模拟。研究结果表明:该比较器在1.8V电源电压下,分辨率为8位,在40MHz的工作频率下,功耗仅为24.4μW,约为同类比较器功耗的1/3。
To reduce power dissipation of a sigma-delta analog-to-digital converter,a new high-speed and low-power dissipation CMOS preamplifier-latch comparator,which is suitable for use in a sigma-delta analog-to-digital converter,was presented in CMOS 0.18μm technology.The comparator consists of a reference voltage generation circuit,a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler.The output sampler circuit consists of a full transmission gate（TG）and two inverters.The use of this sampling stage results in the reduction in the power dissipation of the high-resolution comparator.Hspice simulations of the proposed circuit in a UMC 0.18μm standard CMOS technology operating at supply voltage of 1.8 V was made.The results show that the resolution is 8 bit and the power dissipation is only 24.4μW at 40 MHz.The power dissipation is about 1/3 of that of the similar comparators.
出处
《中南大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2009年第5期1354-1359,共6页
Journal of Central South University:Science and Technology
基金
国家自然科学基金资助项目(60206006)
教育部新世纪优秀人才计划项目(NCET-05-0851)
教育部科技创新工程重大项目培育资金资助项目(708083)
西安应用材料创新基金资助项目(XA-AM-200701)
