摘要
一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。
This paper presents a Σ-Δ fractional-N frequency synthesizer for 434/868 MHz FSK/OOK transmitter.Direct digital modulation of PLL is the transmitter architecture adopted.The FSK modulation is realized by switching between two different division factors,while OOK modulation is implemented with a switch to control the pre-power amplifier.Current controllable voltage-controlled oscillator（VCO）and on-chip differential-to-single converter are exploited to reduce the cost and power of the transmitter IC.The design of divide-by-two circuit （DTC） is also analyzed. The measurement results show that the phase noise is -75 dBc/Hz, -104 dBc/Hz, and -131 dBc/Hz at 10 kHz, 100 kHz, and 3 MHz offset with carrier centered at 868 MHz, respectively. The VCO presents a phase noise of -108 dBc/Hz@100 kHz offset. The measured ad- jacent channel power ratio （ACPR） for 100 kHz channel is less than -50 dBc. The 2 mm^2 transmitter is fabricated with 0.35 μm RF CMOS process. The frequency synthesizer consumes 12. 5 mA from a 2.5 V voltage supply.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2009年第3期383-387,共5页
Research & Progress of SSE
