摘要
在比较反转触发器（TFF）的各种结构的基础上,给出了一种单时钟信号控制实现超高速分频的电路结构,以及具体设计过程。分频器使用动态负载,输出两路互补信号。采用SMIC 0.18um 1P6M CMOS工艺,在电源电压为1.8V的情况下,仿真实现了工作速度10GHz（可工作频率范围为1-13.5GHz）、功耗仅为3.1mW的二分频器,可用于超高速锁相环、时钟数据恢复设计中。
On the basis of comparing to each kind of structure of toggle flip-flop （TFF）,a super-high speed frequency divider circuit structure and it＇s specific design process is presented, which controlled by single clock signal to achieve. The divider output two channels of complementary signals, with dynamic load. Based on SMIC 0.18um 1P6M CMOS, the device is simulated with software of Cadence-Spectre. Simulation shows that, with a 1.8V supply voltage, the frequency divider operates well in the frequency range from 1GHz to 13.SGHz, only 3.1mW power consumption. This frequency diyider can be used to the circuit design of high speed phaselocked loop and clock and data recovery.
出处
《微计算机信息》
2009年第17期286-288,共3页
Control & Automation
基金
<光纤通信中电子色散补偿机制的研究与硬件实现>
国家自然科学基金(60776027)
关键词
CMOS分频器
反转触发器
单时钟信号
动态负载
CMOS frequency divider
Toggle flip-flop
Single clock signal controlling
Dynamic loading
