摘要
通过对乘法器的优化设计,使得模块面积较原面积减少了10%。该乘法器采用CSD编码和Horner法则(Horner's scheme)。在确定硬件实现方案的过程中,通过比较串联累加结构和循环累加结构面积,找到面积的最佳优化点。整个模块采用VHDL设计,并用Mentor公司Modelsim工具进行仿真,采用Synopsys公司综合工具Design Compiler进行面积分析。
The hardware design of multiplier is described,through the optimized method,the total area is cut down about 10%.This multiplier uses canonical signed digit and Horner＇s scheme.In the implementation decision,comparing areas of cascaded adders structure and accumulated structure,find out the optimizing point.The multiplier is designed by VHDL,using Modelsim of Mentor to run the simulation anD USING DESIGN COmpiler of Synopsys company to run synthesis.
出处
《计算机工程与设计》
CSCD
北大核心
2009年第9期2108-2110,共3页
Computer Engineering and Design
