摘要
本文介绍了用常见的中、小规模集成电路设计成高速 A/D 变换器。同时又利用了它的并行传输数字量的速度大大于它本身变换速度的特点,设计了两路在时序上采用相差半个周期来对输入模拟信号交替采样,使 A/D 变换器变换速度达到1MHz 以上。线路实验证明该设计是正确的,实验结果是理想的。并有广泛的使用价值。
This paper introduces a method of designing high-speed A/D converters by using common medium and small integrated circuits.Since the speed of a parallel-multiplex digit is greater than the conversion speed,we can use this characteristic to design two A/D converters of up to 1 MHz, one for each path.This operation system is designed to increase the sequen- tial sampling speed by effectively utilizing these two A/D converters.The- se converters are driven separately at the highest speed of 1 MHz,and sta- ggered by half a cycle in A/D timing to achieve the same result as if sig- nals were sampled by an A/D converter operating at 2 MHz.Circuit test sho- ws that the design is reasonable,and it has a wide range of applications.
出处
《中国民航大学学报》
CAS
1989年第2期16-20,共5页
Journal of Civil Aviation University of China
关键词
A/D
变换器
交替采样
逐次逼近比较
A/D
变换器
A/D converter
staggering sample
successive approximate comparative A/D converter
