摘要
介绍了IP流分类器的设计和实现方法,采用SOPC的思想,在FPGA上实现了C8051功能、MAC模块、TCAM模块等,通过PHY芯片的RGMII接口与FPGA实现的MAC模块通信捕获IP数据包,使用TCAM模块对IP数据包进行分类。整个设计采用硬件描述语言Verilog HDL来实现,通过仿真和实验证实该设计对实现高速IP流分类功能是可行的。
A method of the design and implement for IP flow classifier is introduced in the paper. By applying the ieads of SOPC, the C8051 functions, MAC module, TCAM module and etc. are realized in the Field Programable Gate Array (FPGA) chip The MAC module captures IP packets by the RGMII interface which is connected with the exterior PHY chip, thus the TCAM module classifies those IP packets. The entire design is achieved by the Hardware Description Language——Verilog HDL. The simulation and experimental results show the design is reasonable for high speed IP flows classified.
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2007年第S3期1362-1365,共4页
Journal of University of Electronic Science and Technology of China
基金
教育部科学技术研究重点项目(00053)
广西省自然科学基金(桂科基0575094)
