摘要
提出了基于相位合成法设计的一种简单高性能的时钟占空比调节器PB-DCC(Phase-Blending Duty-Cycle Corrector),用以产生系统需要的高质量时钟。此电路不包含任何反馈环路,根据数控延迟线和脉冲电路的特性采用纯数字方式实现。经0.13μm工艺绘制版图并提取参数后的SPICE模拟结果表明该占空比调节器在200MHz～400MHz频率范围内工作稳定,对占空比在10%～90%范围内的时钟能进行高精度的调节,输出时钟占空比偏离50%在2%以内。
A simple Phase- Blending Duty -Cycle Corrector （PB -DCC） using phase blending, is presented in this paper with high performance to produce high - quality clocks that many systems need. It has no feedbacks, which is full - digital and realized according the features of digital delay lines and pulse generators. When designed with a 0. 13 μm CMOS technology, extracting parameters from the layout our SPICE simulation has indicated that PB - DCC works reliably with the acceptable frequency ranges from 200MHz to 400MHz, and the clock dutycycle which is from 10% to 90% can be corrected with high accuracy, the deviation is below 2% compared to 50%.
出处
《微处理机》
2008年第6期14-16,共3页
Microprocessors
基金
东莞市科研发展基金项目(2005D049
2006D011)
2006年东莞市科技计划项目"射频识别芯片的研究与开发"
湖南省高校科研项目(06D064)资助
关键词
占空比调节
相位合成
无偏时钟
数控延迟线
Duty - cycle correction
Phase - blending
Noskew clock
Digital delay line
