摘要
随着多电平技术的发展,开关数量急剧增加.对于超过三电平的电路结构,现有的嵌入式处理器本身提供的PWM通道显然不够用,而CPLD具有I/O口多、设计灵活、规模大和速度快的优点,为此本文采用DSP+CPLD方式,设计了多电平变换器用脉冲发生器实现方案.详细介绍了方案设计方法和特点,并给出了部分实验结果.
With the development of multi-level technology, the number of switches in system increased quickly. For more than three-level structure of the circuit, the available PWM channel existing in embedded processor is is not enough, and the CPLD has the advantage of I/O amount, flexible design, large scale and quick speed. So this paper design a multilevel converter pulse generator based on DSP and CPLD. This paper introduced design and features in detail, and gives some of the experiment results.
出处
《河北工业大学学报》
CAS
北大核心
2009年第1期61-66,共6页
Journal of Hebei University of Technology
