摘要
解同步电路设计方法可以与现有EDA工具较好地兼容,可以极大地提高异步电路的设计效率.基于解同步电路的抽象模型——控制图,提出了一种解同步电路优化设计方法,优化过程由解同步电路的性能评价函数作为指导,在不影响电路性能的前提下有效地减小电路控制通路的面积.选取了一系列标准测试电路进行了实验,最终解同步电路控制通路所需的局部控制器数量减少了54%,C门的数量减少了76.3%.采用该设计方法,设计实现了0.35μm工艺条件下的32位解同步乘法器,实验结果表明,相对于传统的解同步电路设计方法,提出的优化设计方法可以在保持电路性能的前提下有效地减小电路的面积.
De-synchronous design method, which is compatible with the traditional EDA tools, can greatly improve the design efficiency and decrease the design difficulties of asynchronous circuits. An optimizing design method of de-synchronous circuit based on an abstract model called control graph is presented in this paper. Control graph is an abstract model of de-synchronous circuit. The core step of this optimizing design method is to combine the local controllers in the control path, and a proof has also been given that this combining procedure can preserve the functional equality of this circuit. Through this design method; the area of the control path ean be markedly reduced. This optimizing design method takes the performance evaluation function as its heuristic function, so there is not any penalty on performance. Because this optimizing problem is an NP-hard problem, an approximate algorithm is introduced. To demonstrate the results of this algorithm, it has been applied to a set of benchmark circuits. According to the results, the number of local controllers is decreased 54%, and 76.3% of C-elements required to construct handshake circuit are removed. Finally, a 32-bits desynchronous multiplier in 0.35μm process is designed with this optimizing design method. Compared with the traditional design method of de-synchronous circuit, this optimizing design method will lead to smaller circuit without any penalty in performance.
出处
《计算机研究与发展》
EI
CSCD
北大核心
2009年第2期329-337,共9页
Journal of Computer Research and Development
基金
国家"八六三"高技术研究发展计划基金项目(2007AA01Z101)
国家自然科学基金项目(90407022
60873015)~~
关键词
解同步电路
异步电路
性能评价函数
控制图
时延PETRI网
de-synchronous circuit
asynchronous circuit
performance evaluation function
control graph
timed Petri-net
