摘要
文章基于一种较新颖的纠3错BCH码逐步译码算法和结构原型,提出了BCH译码器的完整实用化结构,采用FPGA设计并实现了纠3错BCH(31,16)译码器。该译码方案的特点是主体结构通用、资源占用少、运行速度高,非常适合于需要对传输帧的帧头实施特殊保护的数据传输应用场合。
Based on a novel step-by-step decoding algorithm and its structure prototype for triple-error-correcting BCH codes, a complete and practical structure for BCH decoder is presented and an FPGA-based BCH（31,16） decoder designed. The decoding scheme is characterized by universal core structure, small device utilization cost and high speed, and thus are very suitable for the data transmission applications where the frame header needs a special protection from the corruption by noises.
出处
《空间电子技术》
2008年第4期60-63,共4页
Space Electronic Technology
关键词
BCH译码
纠3错
FPGA
BCH decoding Triple-error-correcting FPGA
