摘要
提出了一种以小数分频锁相环作为数控振荡器的全数字锁相环架构.该设计具有输出频率高,抖动小等优点.该设计在UMC0.13μm CMOS工艺中实现,版图面积为0.2mm2,最高输出频率可以达到1GHz以上,测量的输出时钟抖动RMS值为32.36ps.
An all-digital PLL in which the NCO is based on a fractional-N PLL is presented. High performance including the high frequency and low jitter of the output clock is obtained. It has been implemented in the UMC 0.13μm CMOS process. The layout area is about 0.2 mm^2, the output clock frequency can be up to 1GHz, the measured output clock jitter is 32.36ps.
出处
《微电子学与计算机》
CSCD
北大核心
2008年第12期25-28,共4页
Microelectronics & Computer
基金
安徽省优秀青年科技基金(06042086)
