摘要
为在编译过程中估计程序在可重构器件上的执行时间,进而进行软硬件代码划分,需要将程序中所有基本块映射到可重构器件上,然后使用逻辑综合或其他方法计算其硬件执行时间,为此提出一个离线布局算法完成基本块的映射工作,同时使用基于IP核的代码转换机制完成从基本块数据流图到布局算法所需任务图的转换.实验结果表明,虽然布局算法的结果是局部最优解,同Xilinx ISE中的布局器相比,生成电路的最大工作频率平均低6.891%,面积大4.016%,但布局过程所需时间缩短了5个数量级,从而极大地减少了整个编译过程所需时间.
In order to estimate a program＇s execution time on reconfigurable devices and perform hardware software code partition, an offline placement algorithm is proposed to map all the basic blocks onto reconfigurable devices, so that logical synthesis or other methods can be used to estimate the generated circuits＇ execution time. Also an IP-Core based code transformation method is used to convert the basic blocks＇ data flow graphs into task graphs which are the inputs of the placement algorithm. Experiments show that although the placement result is locally optimal and that the generated circuits are 6. 891% slower and 4. 016% larger compared with the placer of Xilinx ISE toolset, the proposed algorithm can execute 10^5 times faster, which will greatly reduce the compiler＇s total execution time.
基金
高校博士点基金(20050358040)
安徽省自然科学基金(070412030)资助
关键词
可重构计算
布局算法
代码转换机制
reconfigurable computing
placement algorithm
code transformation
