摘要
提出了一种高效数字下变频器(DDC)实现方法.基于4倍中频采样技术和多相抽取半带滤波结构改进的高效DDC实现结构,相当于仅使用了一个多相抽取半带滤波器实现了I,Q两路信号的输出,降低了运算复杂度,资源节省79%,功耗降低约60 mW.设计实例验证了该方法的正确性与高效性.
An improved efficient implementation method of digital down converter （DDC） in radio monitoring receivers is presented. Based on the sampling technique in which the sampling frequency is 4 times as high as the intermediate frequency and the use of polypahse decimation half band filter architecture, the improved architecture of high-efficiency DDC can be realized by using just one polyphase decimation half band filter to acquire the outputs of in-phase and quadrature in some sense. The improved method decreases the complexity of computation, reduces the burden of calculation and accumulated error. Resources of FPGA is saved 79% and the power consumption of the system is reduced about 60 mW. One design example is given and the results proved the validity and efficiency of the improved DDC structure.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2008年第10期906-909,共4页
Transactions of Beijing Institute of Technology
关键词
数字下变频器
多相结构
半带抽取滤波器
4倍中频采样
digital down converter （DDC）
polyphase structure
half band decimation filter
4-times-IF sampling
