摘要
由于SoC结构的复杂性,必须考虑采用多种可测性设计策略。从功能测试的角度出发,提出了一种基于复用片内系统总线的可测性设计策略,使得片内的各块电路都可被并行测试。阐述了其硬件实现及应用测试函数编写功能测试矢量的具体流程。该结构硬件开销小,测试控制过程简单,可减小测试矢量规模,已应用到一种基于X8051核的智能测控SoC,该SoC采用0.35μm工艺进行了实现,面积为4.1 mm×4.1 mm,测试电路的面积仅占总面积的2%。
Because of the complexity of system on chip （SoC） , different structures and strategies for SoC test must be considered. From the standpoint of function test, a design-for-testability （DFT） strategy based on system reusable bus is presented, which feasibly achieves parallel test for all modules of SoC. The strategy is applied to an intelligent measurement SoC based on X8051 core. The design of the test circuit and the flow of producing the functional test set are described in detail. The simulation results show that this test architecture causes less silicon area, is easily controlled, decreases test vectors and need less test time. The SoC is fabricated in 0. 35 μm COMS process, the area is 4. 1 mm× 4.1 mm, and the test area is only about 2% of the whole chip.
出处
《中国电子科学研究院学报》
2008年第5期520-523,528,共5页
Journal of China Academy of Electronics and Information Technology
