摘要
提出一种针对H.264标准的CABAC解码器的硬件加速器的设计方案。通过采用高效的状态机和良好的SRAM组织结构,使平均解码速率达每周期1bit,可以解码基于高档次的H.264码流,实现对高清码流(1920×1088)的实时解码,在中芯国际0.18μm工艺标准单元库的基础上进行综合,面积占47444门,工作时钟频率达196MHz。
This paper proposes a design scheme of hardware accelerator for CABAC decoder in H.264. It develops an efficient FSM and SRAM system so that the decoder can generate I bit every cycle, and it is capable of decoding High Profile（HP） video stream, achieving the requirement of real-time decoding. An ASIC implementation of the design is carried out in a 0.18 um standard cell library of silicon technology, the estimated frequency is 196 MHz and the area includes 47 444 gates.
出处
《计算机工程》
CAS
CSCD
北大核心
2008年第19期236-238,241,共4页
Computer Engineering
