期刊文献+

一种共游程码的测试数据压缩方案 被引量:5

A Scheme of Test Data Compression Based on Sharing-Run-Length Code
下载PDF
导出
摘要 提出了一种新的基于游程编码的测试数据压缩/解压缩的算法:共游程码(SRLCS)编码,它在使用较短的代码字来代替较长的游程的传统游程编码基础上,进一步充分利用了相邻游程之间的相关性,使用一位来代替与前一游程相同的整个后一游程,这样整个后一游程可以用一位来表示,达到从多位到一位的转换,进一步压缩了测试数据.由于测试数据中存在大量的无关位,对无关位适当的赋值,可以增加连续游程长度相同的概率,提出了一种针对共游程码的无关位填充算法.理论分析和实验结果证明该方案具有高数据压缩率、硬件实现简单等特点. One of the major challenges in testing integrated circuits is dealing with the large test data size. To reduce the volume of test data, several test data compression schemes have been presented. But all of these schemes do not explore the relationship between consecutive runs. So a new scheme of test data compression/decompression, namely sharing-run-length code scheme (SRLCS) is presented, which is based on run length coding. It explores further the relationship between consecutive runs on the basis of traditional run length coding characteristic which uses shorter eodeword to represent longer run length. Thus, only 1 bit needs to represent the whole later run in immediate two runs whose lengths are the same in this scheme. ATPG tools generate test patterns with many don't care bits, which are 95% to 99% of the bits in test data for large industrial circuits. So filling the don't care bits in test data appropriately can increase the probability of the consecutive runs whose lengths are the same. A strategy of filling don't care bits is also proposed for this scheme. Compared with other schemes, this scheme has some characteristics, such as high compression ratio and easy control and implementation. Theoretical analysis and experimental results for the Mintest test set of ISCAS- 89 benchmark circuits show that the proposed scheme is a very efficient compression method.
出处 《计算机研究与发展》 EI CSCD 北大核心 2008年第10期1646-1653,共8页 Journal of Computer Research and Development
基金 国家自然科学基金重大研究计划基金项目(90407008) 国家自然科学基金重点项目(60633060) 安徽省教育厅自然科学基金项目(KJ2008B031)~~
关键词 测试数据压缩 游程编码 Golomb码 FDR码 交替游程码 共游程码 test data compression run length coding Golomb code frequency-directed run-length code alternating run-length code sharing run-length code
  • 相关文献

参考文献15

  • 1Touba N A. Survey of test vector compression techniques [J]. IEEE Design & Test of Computers, 2006, 23 (4): 294- 303 被引量:1
  • 2Xiang D, Zhao Y, Chakrabarty K, et al. A reconfigurable scan architecture with weighted scan-enable signals for deterministic BIST [J]. IEEE Trans on Computer Aided Design of Integrated Circuits and Systems, 2008, 27(6): 999- 1012 被引量:1
  • 3Chandra A, Chakrabarty K. Test data compression and decompression based on internal scan chains and Golomb coding [J]. IEEE Trans on Computer Aided Design of Integrated Circuits and Systems, 2002, 21(6): 715-722 被引量:1
  • 4Chandra A, Chakrabarty K. Low-power scan testing and test data compression for system-on-a- chip [J]. IEEE Trans on Compute-Aided Design of Integrated Circuits and Systems, 2002, 21(5): 597-604 被引量:1
  • 5Chandra A, Chakrabarty K. Test data compression and test resource partitioning for system on a chip using frequency directed run-length (FDR) codes[J]. IEEE Trans on Computers, 2003, 52(8): 1076-1088 被引量:1
  • 6Chandra A, Chakrabarty K, Medina R A. How effective are compression codes for reducing test data volume? [C] //Proc of the 20th IEEE of VLSI Test Symposium (VTS 2002). Los Alamitos, CA: IEEE Computer Society, 2002: 91-96 被引量:1
  • 7Gonciari P T, A1-Hashimi B M, Nicolici N. Variable length input Huffman coding for system-on-a-chip test [J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(6):783-796 被引量:1
  • 8梁华国,蒋翠云.基于交替与连续长度码的有效测试数据压缩和解压[J].计算机学报,2004,27(4):548-554. 被引量:70
  • 9El- Maleh A H. Test data compression for system-on-a-chip using extended frequency-directed run length code [J]. IET Computers & Digital Techniques, 2008, 2(3): 155-163 被引量:1
  • 10方建平,郝跃,刘红侠,李康.应用混合游程编码的SOC测试数据压缩方法[J].电子学报,2005,33(11):1973-1977. 被引量:20

二级参考文献38

  • 1韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350. 被引量:27
  • 2A Jas,J Ghosh-Dastidar,N A Touba.Scan vector compression/decompression using statistical coding[A].Proceeding of 17th IEEE VLSI Test Symposium[C].Dana Point,California,USA,1999.114-120. 被引量:1
  • 3A Chandra,K Chakrabarty.System-on-a-Chip test data compression and decompression architectures based on Golomb codes[J].IEEE Trans.on CAD of Integrated Circuits and System,2001,20(3):355-368. 被引量:1
  • 4A Chandra,K Chakrabarty.Frequency-directed run length (FDR) codes with application to system-on-a-chip test data compression[A].Proceeding of 20th IEEE VLSI Test Symposium[C].Marina Del Rey,California,USA,2001.42-47. 被引量:1
  • 5A Chandra,K Chakrabarty.Reduction of SOC test data volume,scan power and testing time using alternating run-length codes[A].Proceeding of IEEE/ACM,Design Automation Conference[C].New Orleans,Louisiana,USA,2002.673-678. 被引量:1
  • 6A Chandra,K Chakrabarty.How effective are compression codes for reducing test data volume[A]?Proceeding of VLSI Test Symposium[C].Monterey,California,USA,2002.91-96. 被引量:1
  • 7L Li,K Chakrabarty.Test data compression using dictionaries and fixed-length indices[A].Proceeding of IEEE VLSI Test Symposium[C].Napa Valley,California,USA,2003.219-224. 被引量:1
  • 8Yinhe Han,Yongjun Xu,Xiaowei Li.Co-optimization for test data compression and testing power based On variable-tail code[A].Proceeding of 5th International Conference on ASIC[C].Beijing,P R China,2003.105-108. 被引量:1
  • 9Yinhe Han,Yongjun Xu,Huawei Li,Xiaowei Li,A.Chandra.test resource partitioning based on efficient response compaction for test time and tester channels reduction [A].Proceeding of Asian Test Symposium[C].Xi'an,ShanXi,P R China,2003.440-445. 被引量:1
  • 10K Miyase,S Kajihara,I Pomeranz,M Reddy.Don't-care identification on specific bits of test patterns[A].Proceeding of International Conference on Computer Design[C].Freiburg,im Breisgau,Germany,2002.194-199. 被引量:1

共引文献87

同被引文献65

引证文献5

二级引证文献21

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部