摘要
文章设计了一款完全集成的高性能4阶电荷泵锁相环。根据系统性能要求，该锁相环的环路滤波器选用3阶无源低通滤波，其他模块在典型结构的基础上采取了改进措施以获得高性能。首先，利用MATLAB进行系统建模，获得锁定时间和环路参数；然后给出了关键电路的结构以及前、后仿真的结果。在SMIC0．35μm 2P3M CMOS工艺条件下，该锁相环的正常工作范围为60～640MHz，400MHz时周期到周期抖动为96ps，面积为0．38mm^2。内嵌本电路的一种DAC芯片已交付数据，成功参加MPW项目流片。
This paper presents a high performance fourth order CPPLL. Considering the system performance, a third order loop filter is used in the CPPLL, and some improvements are made based on the representative structure of other modules. First, a system model is constructed with the MAT- LAB, and the locking time and the loop parameters are obtained through simulation. Then the critical circuit structure and simulation result are shown. The CPPLL layout is completed through 0.35 μm 2P3M of CMOS technology and its area is 0.38 mm^2. The PLL is able to generate clock signals from 60 MHz to 640 MHz. When it is up to 400 MHz, the cycle-to-cycle jitter is 96 ps. One kind of DAC using this design has participated in the MPW project.
出处
《合肥工业大学学报（自然科学版）》
CAS
CSCD
北大核心
2008年第8期1326-1329,共4页
Journal of Hefei University of Technology：Natural Science
基金
国家部委预研基金资助项目
