摘要
“异或”门电路目前已作为基本门电路使用，但组合逻辑电路ＣＡＤ大多采用以“与非”、“或非”等为基本器件的设计技术。基于“异或”门的组合逻辑化简ＣＡＤ发展了传统的设计方法，把“异或”门作为基本逻辑门，研究出计算机自动逻辑设计的实用方法。对于某些逻辑设计，进一步简化了电路，使电路成本降低，可靠性提高，同时减少了门电路的级数，提高了电路的工作速度。
XOR gate is used as basic element now, but the desgin technique using NAND or NOR gates as basic element is still in use. Function minimization of combinational logic CAD based on XOR gates develops traditional design method. XOR gates are used as basic logic gates, a practical method for computer automatic logic design is developed. To some logic design problems it can go a step further to simplify circuit and cut down cost and improve reliablity. Besides, circuit levels are reduced and operation speed is increased.
出处
《大庆石油学院学报》
EI
CAS
北大核心
1997年第4期53-56,共4页
Journal of Daqing Petroleum Institute
关键词
组合逻辑电路
门电路
异或门电路
CAD
CAD, combinational logic circuit, Karnaugh map, XOR, function minimization
