摘要
可编程逻辑器件(PLD)在嵌入式系统中的应用越来越广泛。文中针对PLD与高速嵌入式单片机AVR间的通信,设计了一种采用读写方式的总线接口模块,用硬件编成语言VHDL在Altera公司的MaxII系列器件EPM570中实现,通过仿真验证其能够完全满足通信功能;并简要介绍了PLD开发的流程。
Programmable Logic Device （PLD）is applied to embedded system more and more popularly. The communication between PLD and high-speed embedded single-chip AVR is discussed in this article. A bus interface for Reading and Writing is designed and implemented by EPM570 （ Altera＇s Max II family） in VHDL, the function of which is expected by simulation. The development process of PLD is presented.
出处
《微计算机信息》
北大核心
2008年第17期223-225,共3页
Control & Automation
基金
教育部科学技术研究重点项目(104086)
