摘要
目前存在的可逆电路综合方法大多只适用于输入输出相对较小的电路,而且忽略了路径延时的影响,无法应对集成电路日益复杂的趋势.为了使综合方法能够适用于大规模可逆电路,本文采用矩阵模型和符号代数作为理论基础,提出了一种符号综合方法,在考虑面积、延时、串扰等约束下利用成本函数来指导综合过程.实验结果表明利用这种启发式算法与现有的综合方法相比,在面积上所得结果近似,而总串扰得到了10.3%的改善,其路径延时要减少5%到20%之多,并且从CPU时间和存储开销上都显示出该算法的优势,有能力在有效的时间内实现大规模可逆电路的综合.
Presently existing synthesis methods for reversible circuits were applicable only to reversible circuits with small numbers of inputs and outputs and bad neglected the impact of path delay, which could not meet the complex design. The heuristic Synthesis algorithm is presented in this paper. Based on matrix model and symbolic algebra, this paper offers a symbolic synthesis method and performs delay and crosstalk optimization simultaneously. Using the cost function the method steers the synthesis process, which considers multiple optimization objectives, including area, delay and crosstalk. The proposed algorithm was tested on a set of reversible benchmarks. Compared with existing synthesis methods, the algorithm reduces crosstalk by 10.3 % and path delay by 5 - 20 %. It has obvious advantages for CPU time and memory cost. The method can handle large scale reversible circuits in reasonable time.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2008年第5期1029-1034,共6页
Acta Electronica Sinica
基金
国家自然科学基金(No.60273081)
关键词
逻辑综合
可逆电路
延时
串扰
logic synthesis
reversible circuits
delay
crosstalk
